Dual function voltage and current mode differential driver

ABSTRACT

A dual function differential driver includes a voltage mode differential driver portion and a current mode differential driver portion. Control circuitry is connected to the voltage mode differential driver portion and the current mode differential driver portion. The control circuitry switches the dual function differential driver between operation as a voltage mode differential driver and operation as a current mode differential driver.

FIELD OF INVENTION

This application is related to the differential drivers.

BACKGROUND

Differential drivers are employed for a variety of functions, such as to provide parallel data to serial data conversion. For example, they may be used to convert a parallel 10-bit digital data signal to a serial 1-bit digital data signal. Also, differential drivers may be employed to convert 1-bit serial digital data signal, (e.g., a rail-to-rail digital signal swinging from 0 V to VDD), to a pair of differential analog signals that meet an electrical specification of a transmitter for a relevant signaling standard.

High speed input/output (I/O) interfaces such as serial-ATA (SATA) require a transmitter to meet different rise and fall (rise/fall) time specifications depending on the generation specification they are operating under. The generation one (Gen1) SATA specification requires a 1.5 Gb/s data rate, while the generation two (Gen2) specification requires a 3 Gb/s data rate, and generation three (Gen3) specification requires a 6 Gb/s data rate. At the same time, the transmitter should also meet a maximum of 20 ps differential skew specifications. The transmitter output signal incurs a larger loss on the transmitting channel at the Gen3 data rate than at the Gen1 data rate due to the limited bandwidth of the channel. To compensate for this channel loss, the transmitter has to output a larger amplitude signal at the Gen3 data rate than at Gen1 data rate.

The rise/fall time specification of SATA Gen3 is from 33 ps to 68 ps, Gen2 is from 67 ps to 136 ps, and Gen1 is from 100 ps to 273 ps. At the Gen3 data rate, the transmitter power consumption may be of concern, particularly when multiple lanes of transmitters are running at a high speed at the same time. Therefore, a differential driver that is effective for transmission at one rate may not be as effective at other rates. The two differential drivers that are commonly used are voltage-mode differential drivers and current-mode differential drivers.

A voltage-mode differential driver may be utilized when running at high speeds, such as the SATA Gen3 data rate, because it consumes lower power than a current-mode differential driver. However, when the same voltage-mode differential driver runs at a relatively low speed, such as the SATA Gen1 data rate, which is four times slower than the Gen3 data rate, the drive strength of the voltage-mode driver has to be weakened by many times to slow down the output signals in order to meet the slower rise/fall time requirement of the Gen1 specification.

To weaken the drive strength, the majority of the transistors in a voltage-mode differential driver have to be turned off. The situation then occurs that a small number of turned-on transistors have to drive a large number of turned-off transistors whose parasitic capacitance is not only very large, but also varies a lot across process, voltage, and temperature (PVT) corners. Therefore, the output rise/fall time of the weakened voltage-mode driver may incur a large variation across PVT corners, which may in turn cause a large mismatch between the rise time and fall time, ultimately causing a large differential skew between the two differential output signals. The transmitter may then not be able to simultaneously meet the rise/fall time and differential skew requirements at the low speed.

A current-mode differential driver, on the other hand, may be utilized to handle the rise/fall time variation and differential skew issues at the low speed, because its rise/fall time is determined by a resistive-capacitance (RC) time constant and therefore has less variation across PVT corners than a voltage-mode differential driver. However, the current-mode driver consumes much more power than a voltage-mode driver when running at high speeds such as the SATA Gen3 data rate. In multiple lane applications, the total power consumption becomes so large that the number of lanes that simultaneously run at the Gen3 data rate may have to be limited.

Therefore, it is challenging to both save power at high speed data rates and also meet different rise/fall times and strict differential skew requirements at low speeds. In Giga-bit high speed circuit design, the less the loading, the faster the circuit can run and the less power the circuit consumes. Therefore, a circuit that occupies a smaller area may operate faster and consume less power when running at a specific speed.

Accordingly, it would be beneficial to provide a differential driver that is capable of effectively operating at both a low speed data rate, such as a Gen1 data rate, when required, while also being capable of operating at a higher speed data rate, such as a Gent or Gen3 data rate when required.

SUMMARY

A dual function voltage and current mode differential driver is disclosed. The dual function voltage and current mode differential driver includes a voltage mode differential driver portion and a current mode differential driver portion. Control circuitry is connected to the voltage mode differential driver portion and the current mode differential driver portion. The control circuitry switches the dual function differential driver between operation as a voltage mode differential driver and operation as a current mode differential driver.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is an example dual function voltage and current mode differential driver;

FIG. 2 is an alternative example of a dual function voltage and current mode differential driver; and

FIG. 3 is another alternative example of a dual function voltage and current mode differential driver.

DETAILED DESCRIPTION OF THE EMBODIMENTS

In order to achieve effective operation at both low data rates and high data rates, a dual function voltage and current mode differential driver may be utilized.

FIG. 1 is an example dual function voltage and current mode differential driver 100. The dual function voltage and current mode driver 100 includes a driver portion 110 and bias and control circuitry 120. The driver portion 110 includes a plurality of transistors, designated M₁, M₂, M₃, M₄, M₅, M₆, M₇, and M₈, and resistors R₇ and R₈. In this example, transistors M₁, M₂, M₆, M₇, and M₈ are P-metal oxide transistors (PMOS) transistors and transistors M₃, M₄, and M₅ are NMOS transistors. The bias and control circuitry 120 includes bitline outputs vbn (bias voltage/enable), cml_en_b (current mode logic enable), and tri_en_b (tri-state mode enable). The bias and control circuitry receives an input in the form of a mode and en (enable) bitline that instructs it to switch the driver portion 110 between operation as a current-mode differential driver and a voltage-mode differential driver.

In the example shown in FIG. 1, PMOS transistors M₆, M₇, and M₈ have their sources connected to the supply voltage (VDD). The gate of M₆ is connected to the tri_en_b bitline, and the gates of M₇ and M₈ are connected to the cml_en_b bitline. The sources of transistors M₁ and M₂ are connected to the drain of transistor M₆. The sources of transistors M₃ and M₄ are connected to the drain of transistor M₅. The gates of transistors M₁ and M₃ are connected to a high input line (in_h) and the gates of transistors M₂ and M₄ are connected to a low input line (in_l). The drains of transistors M₁ and M₃ are connected to a low output line (out_l) and the drains of transistors M₂ and M₄ are connected to a high output line (out_h). The gate of transistor M₅ is connected to vbn and the source is connected to ground. In the voltage-mode differential driver configuration, transistor M₅ turns on as a switch, while in the current-mode configuration, transistor M₅ supplies tail current to the source coupled current-mode driver. Resistor R₇ is connected on one side to the drain of M₇ and to out_l on the other side. Resistor R₈ is connected to the drain of M₈ on one side and to out_h on the other side.

The input lines in_l and in_h are high-speed differential input signals, where the voltage changes from zero volts (0 V) to VDD. The output lines out_h and out_l are high-speed differential output signals. As shown in the example of FIG. 1, the voltage-mode differential driver includes transistors M₁, M₂, M₃, M₄, M₅, and M₆. The current-mode differential driver includes transistors M₃, M₄, M₅, M₇, and Mg and resistors R₇ and R₈. The bias and control circuitry 120 generates the output signals vbn, cml_en_b, and tri_en_b, based on the input signals received.

When en=VDD, the input signal mode will switch the dual function driver between operation as a current-mode differential driver and a voltage-mode differential driver. When en=0V, the en signal will override the mode signal. Accordingly, whether the input signal mode is VDD or 0V, both the bias and control circuitry 120 and the dual function driver 100 will be disabled. The outputs out_h and out_l are placed in a high-impedance state.

An example operation of the dual function voltage and current mode differential driver 100 is as follows. When the bias and control circuitry 120 receives an input indicating that the driver 100 is to operate as a voltage mode driver, the tri_en_b output is set to 0 V, while both vbn and cml_en_b are set to VDD. For example, when en=VDD and mode=VDD, the bias and control circuitry 120 outputs are tri_en_b=0V, vbn=VDD, and cml_en_b=VDD. Alternatively, when en=VDD, and mode=0V, the bias and control circuitry 120 outputs are tri_en_b=0V, vbn=VDD, and cml_en_b=VDD This sets the differential driver 100 into a voltage mode driver. Accordingly, transistors M₅ and M₆ are switched on, while M₇ and M₈ are switched off. In this configuration, when in_h is equal to VDD and in_l is equal to 0 V, out_h will be VDD and out_l will be 0 V. When in_l is equal to VDD and in_h is equal to 0 V, out_l will be VDD and out_h will be 0 V.

When the bias and control circuitry 120 receives an input signal to indicating that the driver 100 is to operate as a current mode driver, it sets vbn to the bias voltage, tri_en_b to VDD, and cml_en_b to 0 V. For example, when en=VDD, and mode=0V, the bias and control circuitry 120 outputs are tri_en_b=VDD, vbn=bias voltage, and cml_en_b=0V. Alternatively, when en=VDD and mode=VDD, the bias and control circuitry 120 outputs are tri_en_b=VDD, vbn=bias voltage, and cml_en_b=0V. This sets the differential driver 100 into a current mode driver. Accordingly, M₅ will switch on and provide tail current for the current mode driver, while M₆ will turn off. Transistors M₇ and Mg are switched on. If in_h is VDD and in_l is 0 V, then M₃ is switched on and M₄ is switched off. Transistor M₁ is also switched off. If in_l is VDD and in_h is 0 V, then M₄ is switched on and M₃ is switched off. Transistor M₂ is also switched off. Since in one case or the other, either M₁ or M₂ is switched off, the out_h and out_l signals will not be shorted by M₁ and M₂. The tail current of M₅ may be referred to as I5 and the resistors R₇ and R₈ may be collectively referred to as ‘R’. Accordingly, when in_h is VDD and in_l is 0 V, then out_h is VDD and out_l is (VDD−I5*R). When in_h is 0 V and in_l is VDD, then out_h is (VDD−I5*R) and out_l is VDD.

When the input to the bias and control circuitry 120 indicates that the dual function driver is to be disabled, tri_en_b is set to VDD, cml_en_b is set to VDD, and vbn is set to 0 V. Accordingly, the outputs out_h and out_l are placed in a high-impedance state, and M₅, M₆, M₇, and M₈ are switched off. The bias and control circuitry 120 and the transistors M₅, M₆, M₇, and M₈ operate as a control circuitry to switch the driver 100 between a voltage mode differential driver and a current mode differential driver.

The example driver 100 depicted in FIG. 1 includes a single signal path from the input lines to the output lines and M₃, M₄, and M₅ are shared between the voltage mode and the current mode driver operation. With respect to the input signal, the high speed input signal in_h and in_l each only drive two transistors. That is, in_h drives M₁ and M₃, and in_l drives M₂ and M₄. Accordingly, the loading that in_h and in_l have in a circuit that achieves the dual function of a voltage mode and current mode driver is greatly reduced.

With respect to the output signal, the high speed output signal out_h and out_l each only see one resistor and the drain diffusion of two transistors as its loading. That is, out_h sees R₇ and the drains of M₁ and M₃, and out_l sees R₈ and the drains of M₂ and M₄. Accordingly, the loading that out_h and out_l have in such a circuit that achieves the dual functions of a current and voltage mode driver is greatly reduced.

FIG. 2 is an alternative example of a dual function voltage and current mode differential driver 200. The driver 200 is similar to the driver 100, and includes a driver portion 210 and bias and control circuitry 220. In the driver 210, an additional transistor M₉ is included. In this example, the drain of the transistor M₆ is connected to the source of transistor M₁, the gate is connected to tri_en_b, and the source is connected to VDD. Similarly, the drain of the transistor M₉ is connected to the source of transistor M₂, the gate is connected to tri_en_b, and the source is connected to VDD. The operation of the driver 200 is similar to the operation described above for the driver 100. However, in this embodiment, when the tri_en_b output is set to 0 V, both M₆ and M₉ are switched on.

FIG. 3 is another alternative example of a dual function voltage and current mode differential driver 300. The dual function voltage and current mode driver 300 includes a driver portion 310 and bias and control circuitry 320. The driver portion 310 of the driver 300 includes a current mode differential driver portion, which includes transistors M₁, M₂, M₃, M₄ and M₅ and resistors R₁ and R₂, and a voltage mode differential driver that includes transistors M₆, M₇, M₈, M₉, M₁₀ and M₁₁. The bias and control circuitry 320 receives an input and outputs a bias output, cml_em_b output, tri_en output, and tri_en_b output.

In the current mode differential driver portion, the sources of transistors M₁ and M₂ are connected to VDD, and the gates are connected to cml_en_b. The drain of M₁ is connected to one end of resistor R₁ and the drain of M₂ is connected to one end of resistor R₂. The sources of transistors M₃ and M₄ are connected to the drain of transistor M₅. The gate of M₃ is connected to in_h, and the drain is connected to the other side of resistor R₁ and out_l. The gate of M₄ is connected to in_l, and the drain is connected to the other side of resistor R₂ and out_h. The gate of M₅ is connected to the bias output of the bias and control circuitry 320 and the source is connected to the reference voltage.

In the voltage mode differential driver portion, the source of transistor M₆ is connected to VDD, and the gate is connected to tri_en_b. The sources of M₇ and M₈ are connected to the drain of transistor M₆. The drains of transistors M₇ and M₉ are connected to each other and out_l. The drains of transistors M₈ and M₁₀ are connected to each other and out_h. The sources of transistors M₉ and M₁₀ are connected to each other and to the drain of M₁₁. The gates of transistors M₇ and M₉ are connected to each other and in_h. The gates of transistors M₈ and M₁₀ are connected to each other and in_l. The gate of M₁₁ is connected to the tri_en output of the bias and control circuitry 320, and the source of is connected to reference voltage.

In operation, when the bias control circuitry 320 receives an input to switch the driver 300 to a voltage mode differential driver, the tri_en_b output is set to 0 V, cml_en_b is set to VDD, and tri_en is set to VDD. This results in transistors M₁ and M₂ being switched off, and disabling the current mode differential portion of the circuit, while transistor M₆ is switched on. In this configuration, when in_h is equal to VDD and in_l is equal to 0 V, out_h will be VDD and out_l will be 0 V. When in_l is equal to VDD and in_h is equal to 0 V, out_l will be VDD and out_h will be 0 V.

When the bias control circuitry 320 receives an input to switch the driver 300 to a current mode differential driver, the tri_en_b output is set to VDD, and cml_en_b is set to 0 V. As a result, transistors M₁ and M₂ are switched on, while transistor M₆ is switched off, disabling the voltage mode differential portion of the circuit. In this configuration, ff in_h is VDD and in_l is 0 V, then M₃ is switched on and M₄ is switched off. If in_l is VDD and in_h is 0 V, then M₃ is switched off and M₄ is switched on. The resistance of R₇ and R₈ may be collectively referred to as ‘R’. The tail current of M₅ may be referred to as I5, and accordingly, when in_h is VDD and in_l is 0 V, then out_h is VDD and out_l is (VDD−I5*R). When in_h is 0 V and in_l is VDD, then out_h is (VDD−I5*R) and out_l is VDD.

Although features and elements are described above in particular combinations, each feature or element can be used alone without the other features and elements or in various combinations with or without other features and elements. The methods or flow charts provided herein may be implemented in a computer program, software, or firmware incorporated in a computer-readable storage medium for execution by a general purpose computer or a processor. Examples of computer-readable storage mediums include a read only memory (ROM), a random access memory (RAM), a register, cache memory, semiconductor memory devices, magnetic media such as internal hard disks and removable disks, magneto-optical media, and optical media such as CD-ROM disks, and digital versatile disks (DVDs).

Suitable processors include, by way of example, a general purpose processor, a special purpose processor, a conventional processor, a digital signal processor (DSP), a plurality of microprocessors, one or more microprocessors in association with a DSP core, a controller, a microcontroller, Application Specific Integrated Circuits (ASICs), Field Programmable Gate Arrays (FPGAs) circuits, any other type of integrated circuit (IC), and/or a state machine. Such processors may be manufactured by configuring a manufacturing process using the results of processed hardware description language (HDL) instructions (such instructions capable of being stored on a computer readable media). The results of such processing may be maskworks that are then used in a semiconductor manufacturing process to manufacture a processor which implements aspects of the present invention. 

1. A dual function differential driver, comprising: a voltage mode differential driver portion; a current mode differential driver portion; and control circuitry connected to the voltage mode differential driver portion and the current mode differential driver portion to switch the dual function differential driver between operation as a voltage mode differential driver and operation as a current mode differential driver, or to disable the dual function differential driver.
 2. The dual function differential driver of claim 1 wherein the control circuitry further comprises a bias and control circuitry and a plurality of transistors, the bias and control circuitry switching at least one of the plurality of transistors to an on state and at least another of the plurality of transistors to an off state.
 3. The dual function differential driver of claim 2 wherein the voltage mode differential driver portion includes a first, second, third, fourth, fifth transistor, and sixth transistor.
 4. The dual function differential driver of claim 3 wherein the current mode differential driver portion includes the third, fourth and fifth transistors, a seventh and eighth transistor and at least one resistor.
 5. The dual function differential driver of claim 4 wherein the bias and control circuitry outputs a dual function bias/enable output, a tristate enable output, and a current mode enable output.
 6. A method for driving a signal, comprising: providing a first differential driver for driving the signal in a first mode; providing a second differential driver for driving the signal in a second mode; determining an operating mode to drive the signal; and switching the operating mode based upon the determination.
 7. The method of claim 6, further comprising enabling the first differential driver and disabling the second differential driver on a condition that the determining the mode to drive the signal is the first mode.
 8. The method of claim 6, further comprising enabling the second differential driver and disabling the first differential driver on a condition that the determining the mode to drive the signal is the second mode.
 9. The method of claim 6, further comprising disabling both the first and second differential drivers on a condition that the determining the mode to drive the signal is not the first or second modes.
 10. The method of claim 6 wherein the first mode is a voltage mode and the first differential driver is a voltage differential driver.
 11. The method of claim 6 wherein the second mode is a current mode and the second differential driver is a current differential driver.
 12. A computer-readable storage medium containing a first set of instructions adapted to create a processor, wherein the processor is configured to implement a second set of instructions, the second set of instructions comprising: a first differential driver code segment for driving a signal in a first mode; a second differential driver code segment for driving the signal in a second mode; a switching code segment for switching the mode of operation between the first and second mode or a disable mode.
 13. The computer-readable storage medium of claim 12 wherein the first mode is a voltage differential driver mode.
 14. The computer-readable storage medium of claim 12 wherein the second mode is a current differential driver mode.
 15. The computer-readable storage medium of claim 12 wherein the switching code segment enables the first differential driver code segment and disables the second differential driver code segment.
 16. The computer-readable storage medium of claim 12 wherein the switching code segment enables the second differential driver code segment and disables the first differential driver code segment.
 17. The computer-readable storage medium of claim 12 wherein the switching code segment disables the first and second differential driver code segments. 